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This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .

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It has been designed for operation in the harsh space environment, and includes functionality pprocessor detect and correct single event upset SEU errors in all on-chip RAM memories.

The NGMP has the following on-chip functions:. Pre-synthesized FPGA programming files are also provided. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. Views Read Edit View history.

LEON3 Processor

The LEON4 processor has the following features:. Archived from the original PDF on This article is about the family of microprocessors. Up to 16 CPU can be used in a multiprocessing configuration.

The LEON3 processor has the following features:.

LEON3 bit processor core | Realtime Embedded

This section and ptocessor subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution. This website requires javascript to function properly.


The model is highly configurable, and particularly suitable for system-on-a-chip SoC designs. More information regarding these models can is available on the Aeroflex Gaisler website. It is highly configurable, and was designed for embedded applications with the following leoj3 on-chip:. Your rating has been changed, thanks for rating!

The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed.

From Wikipedia, the free encyclopedia. The LEON3 template designs can be configured using a graphical tool built on tkconfig from the linux kernel. The LEON4 processor has the following features: Retrieved from ” http: Procwssor the LEON2 -FT design can be extended ,eon3 re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.

It is described in synthesizable VHDL. This page presents the major microprocessors used or to be used in most European space applications. The full source code is available under the GNU GPL license, allowing free and unlimited use proceszor research and education.

For other uses, see Leon disambiguation. For industrial and high-rel applications, ports for VxWorks 5. Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals.

Archived copy as title Webarchive template wayback links Articles lacking reliable references from November All articles lacking reliable references Articles containing Spanish-language text Articles with Curlie links. SnapGear Linux proceasor a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. Branch prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1.


The model is highly configurable, and particularly suitable for system-on-a-chip SoC designs. Airbus Defense leon33 Space. The certification was completed on May 1, LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications. Hardware iCE Stratix Virtex. Flip-flops are protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity bits.

Aeroflex Gaisler – Device: LEON has a dual license model: Another objective was to be able to manufacture in a Single event upset SEU tolerant sensitive semiconductor process. It features the following: It is thus possible to instantiate several processor cores in the same design with different configurations. Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse.

A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration.

It is highly configurable, and was designed for embedded applications with the following features on-chip: